The present invention relates in general to the fabrication and testing of semiconductor wafers. More specifically, the present invention relates to systems, methods and computer program products for performing accelerated semiconductor wafer testing by applying non-destructive, controlled and localized stress to the wafer under test.
In electronics, the term “reliability” is used to describe the probability that a component operating under specified conditions will perform satisfactorily for a given period of time. Scaling semiconductor circuitry to increasingly smaller dimensions impacts the lifetime and reliability of individual devices due to increased fragility, higher power density, more complex devices, and new failure mechanisms. Semiconductor test systems and methodologies have been developed to test the affect on product reliability of a variety of wear-out mechanisms, including, for example, electromigration (EM), gate oxide integrity (GOI), negative bias temperature instability (NBTI), stress migration (SM), and the like.
So-called “accelerated testing” identifies wear-out mechanisms under specific stress conditions, including, for example, increased temperature. Accelerated testing compresses time. For example, performing 100 hours of testing under accelerated stress conditions (e.g., at high temperatures) can be equivalent to 10,000 hours of operation under use conditions.